1. Field of the Invention
This invention relates to the field of data processing, and in particular to data processing using multiple sets of program instruction words.
2. Description of the Prior Art
Data processing systems operate with a processor core acting under control of program instruction words which when decoded serve to generate core control signals to control the different elements in the processor to perform the necessary operations to achieve the processing specified in the program instruction word.
It is known to provide systems that execute program instruction words from two or more instruction sets, with means being provided to switch between use of the different instruction sets. The VAX11 computers of Digital Equipment Corporation have a VAX instruction mode and a compatibility mode that enables them to decode the instructions for the earlier PDP11 computers.
In order to switch between the different instruction sets, an instruction set switch may be hard-wired into the processor core necessitating a physical rewiring of the processor to switch instruction sets. Alternatively, a processor register may be used to specify the current instruction set to be used. In this case, the current instruction set can be selected by the operating software, by writing an instruction set-specifying value to that processor register. However, as described below, this technique requires additional program instruction words, which in turn require extra time during preparation of the software and extra memory space to store the program instruction words.
In order to execute a piece of code, a processor capable of using two or more instruction sets must have two pieces of information:
1) The address of the code in memory; and
2) The instruction set to use (i.e. the instruction set in which the code is written)
Typically, in the previously proposed processors, a call to a routine in a different instruction must be performed as described below.
1) The subroutine call is diverted from its original destination to an automatically generated instruction set selection sequence or veneer.
2) The veneer must then accomplish the following
Save the context of the caller PA1 Select the correct instruction set PA1 Call the original routine PA1 On return from the original routine, select the original instruction set PA1 Restore the callers context. PA1 a processor core having means for executing successive program instruction words of a predetermined plurality of instruction sets; PA1 a data memory for storing program instruction words to be executed; PA1 a program counter register for indicating the address of a next program instruction word in the data memory; PA1 means for modifying the contents of the program counter register in response to a current program instruction word; and PA1 control means, responsive to one or more predetermined indicator bits of the program counter register, for controlling the processor core to execute program instruction words of a current instruction set selected from the predetermined plurality of instruction sets and specified by the state of the one or more indicator bits of the program counter register.
This process can be made relatively transparent to the programmer by use of a conventional software tool called a Linker. However, the process has a five instruction overhead per routine which is called from a different instruction set, and it also introduces a significant processing overhead.